#include "ddr_common.h"

#define CANDS_CTL_REG_BASE 	0X30000000
#define CANDS_PHY_REG_BASE 	0X30001000
#define CANDS_PHY_CORE_REG_BASE 	0X30001500

#define CANDS_CTL_REG_BASE1	0X30800000
#define CANDS_PHY_REG_BASE1	0X30801000
#define CANDS_PHY_CORE_REG_BASE1	0X30801500

#define CANDS_CTL0_(i) (CANDS_CTL_REG_BASE + i*4)
#define CANDS_PHY0_(i) (CANDS_PHY_REG_BASE + i*4)
#define CANDS_PHYCORE0_(i) 	(CANDS_PHY_CORE_REG_BASE + i*4)

#define CANDS_CTL1_(i) (CANDS_CTL_REG_BASE + i*4)
#define CANDS_PHY1_(i) (CANDS_PHY_REG_BASE + i*4)
#define CANDS_PHYCORE1_(i) 	(CANDS_PHY_CORE_REG_BASE + i*4)

#define AON_APB_DPLL0_CFG0	0x40400034
#define AON_APB_DPLL1_CFG0	0X4040003c

#define PMU_APB_PD_PUB0_SYS_CFG     0X402B0050
#define PMU_APB_PD_PUB1_SYS_CFG     0X402B0054
#define PMU_APB_SLEEP_CTRL          0X402B00E8
#define PMU_APB_DDR_SLEEP_CTRL      0X402B00EC
#define PMU_APB_PD_PUBCP_SYS_CFG    0X402B0084

#define AON_APB_CGM_CFG 0x402E0098
#define AON_APB_CGM_CLK_TOP_REG1 0x402E013C
#define AON_APB_PUB_FC_CTRL 0x402E01E0
#define AON_APB_EB_AON_ADD1 0x402E01D0

#define PD_CA53_TOP_CFG     0X402B0000
#define PD_CA53_LIT_MP4_CFG 0X402B0004
#define PD_CA53_LIT_C0_CFG  0X402B000C
#define PD_CA53_LIT_C1_CFG  0X402B0010
#define PD_CA53_LIT_C2_CFG  0X402B0014
#define PD_CA53_LIT_C3_CFG  0X402B0018

#define PD_CA53_BIG_MP4_CFG 0X402B001C
#define PD_CA53_BIG_C0_CFG  0X402B0020
#define PD_CA53_BIG_C1_CFG  0X402B0024
#define PD_CA53_BIG_C2_CFG  0X402B0028
#define PD_CA53_BIG_C3_CFG  0X402B002C

#define SYS_SOFT_RST        0X402B00C4


#define PUB0_SOFT_DFS_CTRL 		0x30018000
#define PUB0_HARD_DFS_CTRL_LO 	0x30018004
#define PUB0_HARD_DFS_CTRL_HI 	0x30018008
#define PUB0_SOFT_DFS_CTRL 		0x30018000
#define PUB0_BIST_TEST_CTRL 	0x30018028
#define PUB0_LP_GEN_CTRL 		0x3001802C
#define PUB0_PURE_SW_DFS_CTRL	0x30018030
#define PUB0_DFS_STATUS			0x30018034

#define PUB1_SOFT_DFS_CTRL 		0x30818000
#define PUB1_HARD_DFS_CTRL_LO 	0x30818004
#define PUB1_HARD_DFS_CTRL_HI 	0x30818008
#define PUB1_SOFT_DFS_CTRL 		0x30818000
#define PUB1_BIST_TEST_CTRL 	0x30818028
#define PUB1_LP_GEN_CTRL 		0x3081802C
#define PUB1_PURE_SW_DFS_CTRL	0x30818030
#define PUB1_DFS_STATUS			0x30818034

#define PUB0_APB_BUSMON_CFG 0x30010004
#define PUB1_APB_BUSMON_CFG 0x30810004

#define PUB0_DFS_BUSMON_BASE 0x300C0000
#define PUB1_DFS_BUSMON_BASE 0x308C0000

#define PUB0_DFS_BUSMON_CFG 		         (PUB0_DFS_BUSMON_BASE)
#define PUB0_DFS_BUSMON_INT_EN 		         (PUB0_DFS_BUSMON_BASE+0x4)
#define PUB0_DFS_BUSMON_INT_CLR 	         (PUB0_DFS_BUSMON_BASE+0x8)
#define PUB0_DFS_BUSMON_INT_STATUS           (PUB0_DFS_BUSMON_BASE+0xC)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_W0       (PUB0_DFS_BUSMON_BASE+0x10)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_W1       (PUB0_DFS_BUSMON_BASE+0x14)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_R0       (PUB0_DFS_BUSMON_BASE+0x18)
#define PUB0_DFS_BUSMON_BDWIDTH_CNT_R1       (PUB0_DFS_BUSMON_BASE+0x1C)

#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F0   (PUB0_DFS_BUSMON_BASE+0x20)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F0  (PUB0_DFS_BUSMON_BASE+0x24)
#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F1   (PUB0_DFS_BUSMON_BASE+0x28)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F1  (PUB0_DFS_BUSMON_BASE+0x2C)
#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F2   (PUB0_DFS_BUSMON_BASE+0x30)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F2  (PUB0_DFS_BUSMON_BASE+0x34)
#define PUB0_DFS_BUSMON_OVERFLOW_TSHOLD_F3   (PUB0_DFS_BUSMON_BASE+0x38)
#define PUB0_DFS_BUSMON_UNDERFLOW_TSHOLD_F3  (PUB0_DFS_BUSMON_BASE+0x3C)
#define PUB0_DFS_BUSMON_BDWIDTH_BASE_NUM     (PUB0_DFS_BUSMON_BASE+0x40)


#define PUB1_DFS_BUSMON_CFG 				 (PUB1_DFS_BUSMON_BASE)
#define PUB1_DFS_BUSMON_INT_EN 				 (PUB1_DFS_BUSMON_BASE+0x4)
#define PUB1_DFS_BUSMON_INT_CLR 			 (PUB1_DFS_BUSMON_BASE+0x8)
#define PUB1_DFS_BUSMON_INT_STATUS  		 (PUB1_DFS_BUSMON_BASE+0xC)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_W0  	 (PUB1_DFS_BUSMON_BASE+0x10)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_W1  	 (PUB1_DFS_BUSMON_BASE+0x14)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_R0  	 (PUB1_DFS_BUSMON_BASE+0x18)
#define PUB1_DFS_BUSMON_BDWIDTH_CNT_R1  	 (PUB1_DFS_BUSMON_BASE+0x1C)

#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F0   (PUB1_DFS_BUSMON_BASE+0x20)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F0  (PUB1_DFS_BUSMON_BASE+0x24)
#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F1   (PUB1_DFS_BUSMON_BASE+0x28)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F1  (PUB1_DFS_BUSMON_BASE+0x2C)
#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F2   (PUB1_DFS_BUSMON_BASE+0x30)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F2  (PUB1_DFS_BUSMON_BASE+0x34)
#define PUB1_DFS_BUSMON_OVERFLOW_TSHOLD_F3   (PUB1_DFS_BUSMON_BASE+0x38)
#define PUB1_DFS_BUSMON_UNDERFLOW_TSHOLD_F3  (PUB1_DFS_BUSMON_BASE+0x3C)
#define PUB1_DFS_BUSMON_BDWIDTH_BASE_NUM     (PUB1_DFS_BUSMON_BASE+0x40)



#define PUB0_AXI_BUSMON0_BASE 0x30020000
#define PUB0_AXI_BUSMON1_BASE 0x30030000
#define PUB0_AXI_BUSMON2_BASE 0x30040000
#define PUB0_AXI_BUSMON3_BASE 0x30050000
#define PUB0_AXI_BUSMON4_BASE 0x30060000
#define PUB0_AXI_BUSMON5_BASE 0x30070000
#define PUB0_AXI_BUSMON6_BASE 0x30080000
#define PUB0_AXI_BUSMON7_BASE 0x30090000
#define PUB0_AXI_BUSMON8_BASE 0x300A0000
#define PUB0_AXI_BUSMON9_BASE 0x300B0000

#define PUB1_AXI_BUSMON0_BASE 0x30820000
#define PUB1_AXI_BUSMON1_BASE 0x30830000
#define PUB1_AXI_BUSMON2_BASE 0x30840000
#define PUB1_AXI_BUSMON3_BASE 0x30850000
#define PUB1_AXI_BUSMON4_BASE 0x30860000
#define PUB1_AXI_BUSMON5_BASE 0x30870000
#define PUB1_AXI_BUSMON6_BASE 0x30880000
#define PUB1_AXI_BUSMON7_BASE 0x30890000
#define PUB1_AXI_BUSMON8_BASE 0x308A0000
#define PUB1_AXI_BUSMON9_BASE 0x308B0000

#define PUB0_AXI_BUSMON_CHN_CFG(x) 		(x*0x10000+PUB0_AXI_BUSMON0_BASE+0x0)
#define PUB0_AXI_BUSMON_DN_RLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0xC)
#define PUB0_AXI_BUSMON_DN_WLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0x14)
#define PUB0_AXI_BUSMON_UP_RLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0x1C)
#define PUB0_AXI_BUSMON_UP_WLATENCY(x)  (x*0x10000+PUB0_AXI_BUSMON0_BASE+0x24)

#define PUB1_AXI_BUSMON_CHN_CFG(x) 		(x*0x10000+PUB1_AXI_BUSMON0_BASE+0x0)
#define PUB1_AXI_BUSMON_DN_RLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0xC)
#define PUB1_AXI_BUSMON_DN_WLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0x14)
#define PUB1_AXI_BUSMON_UP_RLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0x1C)
#define PUB1_AXI_BUSMON_UP_WLATENCY(x)  (x*0x10000+PUB1_AXI_BUSMON0_BASE+0x24)


#define IS_LPDDR3(x)    (((x&0xff000000) == 0x30000000)?TRUE:FALSE)
#define IS_LPDDR2(x)    (((x&0xff000000) == 0x20000000)?TRUE:FALSE)
#define IS_DDR3(x)      (((x&0xff000000) == 0x3F000000)?TRUE:FALSE)
#define IS_2CS(x)       (((x&0x00f00000) == 0x00200000)?TRUE:FALSE)





typedef enum
{
    //lpddr2
    //DRAM_LPDDR2             = 0x20000000,       
    DRAM_LPDDR2_1CS_2G_X32  = 0x20102320,
    DRAM_LPDDR2_1CS_4G_X32  = 0x20104320,
    DRAM_LPDDR2_1CS_8G_X32  = 0x20108320,
    DRAM_LPDDR2_2CS_4G_X32  = 0x20204320,
    DRAM_LPDDR2_2CS_6G_X32  = 0x20206320,
    DRAM_LPDDR2_2CS_8G_X32  = 0x20208320,
    DRAM_LPDDR2_2CS_12G_X32 = 0x20212320,
    DRAM_LPDDR2_2CS_16G_X32 = 0x20216320,

    //lpddr3
    //DRAM_LPDDR3             = 0x30000000,
    DRAM_LPDDR3_1CS_4G_X32  = 0x30104320,
    DRAM_LPDDR3_1CS_6G_X32  = 0x30106320,
	DRAM_LPDDR3_1CS_8G_X32  = 0x30108320,
	DRAM_LPDDR3_2CS_8G_X32  = 0x30208320,
	DRAM_LPDDR3_2CS_16G_X32 = 0x30216320,
	
    //ddr3
    //DRAM_DDR3               = 0x3f000000,
    DRAM_DDR3_1CS_2G_X8_4P  = 0x3f102084, //4-piece 2g bit ddr3 chips, 4 cs bonded into 1 cs, 8g bit together
    DRAM_DDR3_1CS_4G_X8_4P  = 0x3f104084, //4-piece 4g bit ddr3 chips, 4 cs bonded into 1 cs, 16g bit together
    DRAM_DDR3_1CS_8G_X8_4P  = 0x3f108084, //4-piece 8g bit ddr3 chips, 4 cs bonded into 1 cs, 32g bit together
    DRAM_DDR3_1CS_1G_X16_2P = 0x3f101162, 
    DRAM_DDR3_1CS_2G_X16_2P = 0x3f102162, //2-piece 2g bit ddr3 chips, 2 cs bonded into 1 cs, 4g bit together
    DRAM_DDR3_1CS_4G_X16_2P = 0x3f104162, //2-piece 4g bit ddr3 chips, 2 cs bonded into 1 cs, 8g bit together
    DRAM_DDR3_1CS_8G_X16_2P = 0x3f108162, //2-piece 8g bit ddr3 chips, 2 cs bonded into 1 cs, 16g bit together
}DRAM_TYPE_E;

typedef enum
{
/*Driver strength for lpddr1*/
    LPDDR1_DS_FULL,
    LPDDR1_DS_HALF,
    LPDDR1_DS_QUARTER,
    LPDDR1_DS_OCTANT,
    LPDDR1_DS_THREE_QUATERS,
/*Driver strength for lpddr2*/
    LPDDR2_DS_34R3 = 0x0f,
    LPDDR2_DS_40R  = 0x0e,
    LPDDR2_DS_48R  = 0x0d,
    LPDDR2_DS_60R  = 0x0c,
    LPDDR2_DS_80R  = 0x09,
    LPDDR2_DS_120R = 0x08,
    LPDDR2_DS_240R = 0x01,
/*Driver strength for lpddr3*/
    LPDDR3_DS_HZ   = 0x00,
    LPDDR3_DS_34R3 = 0x0f,
    LPDDR3_DS_40R  = 0x0e,
    LPDDR3_DS_48R  = 0x0d,
    LPDDR3_DS_60R  = 0x0c,
    LPDDR3_DS_80R  = 0x09,
    LPDDR3_DS_120R = 0x08,
    LPDDR3_DS_240R = 0x01,

/*Driver strength for ddr3*/
    DDR3_DS_40R   = 0x00,
    DDR3_DS_34R3  = 0x01
}DDR_DS_E;

typedef enum
{
	PHY_SLICE0 = 0,
	PHY_SLICE1 = 1,
	PHY_SLICE2 = 2,
	PHY_SLICE3 = 3,
	PHY_SLICE4 = 4,
	PHY_CORE = 5,
}CANDS_PHY_SLICE_E;


typedef enum
{
	MEM_MR0 = 0,
	MEM_MR1 = 1,
	MEM_MR2 = 2,
	MEM_MR3 = 3,
    MEM_MR4 = 4,
	MEM_MR5 = 5,
	MEM_MR6 = 6,
	MEM_MR8 = 8,
	MEM_MR10 = 10,
}MEM_MR_E;

typedef enum
{
	DDR_CHANNEL_0 = 0,
	DDR_CHANNEL_1 = 1,
}DDR_CHANNEL_NUM_E;


//*****************user define**********
#define DDR_LPDDR3
#define DDR_TYPE DRAM_LPDDR3_1CS_8G_X32
#define DDR_BL  8
#define DDR_DS  LPDDR3_DS_34R3

//#define CANDS_DEF_SETTING

#define ZQINIT_DIS 0
#define WRLVL_EN  1
#define RDELVL_EN 1
#define RDGLVL_EN 1
#define CALVL_EN  1


//**************************************
